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DS38464
3.3V 64K x 40 NV SRAM SIMM
www.maxim-ic.com
FEATURES
* * * * * * * * * 2Mbits organized as a 64K x 40 memory 6 years minimum data retention in the absence of external power Nonvolatile circuitry transparent to and independent of host system Automatic write protection circuitry safeguards against data loss Battery monitor checks remaining capacity daily Fast access time of 70ns Operating VCC range of 3.0V to 3.6V Employs popular JEDEC standard 72position SIMM connector Operating temperature: 0oC to +70oC
PIN ASSIGNMENT
PIN DESCRIPTION
A0 - A15 DQ0 - DQ39 CEA\ WE\ OE\ VCC GND Address Inputs Data Inputs/Outputs Chip Enable Inputs Write Enable Inputs Output Enable Inputs 3.3V Power Supply Ground
DS38464 72-PIN SIMM
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DS38464
DESCRIPTION
The DS38464 is a self-contained 2,621,440-bit, nonvolatile static RAM, which is organized as a 64K x 40 memory. Built using three 64K x 16 SRAMs, one nonvolatile control IC, and one lithium battery, this nonvolatile memory contains all the necessary control circuitry and lithium energy source to maintain data integrity in the absence of power for more than 6 years. The DS38464 employs the popular JEDEC standard 72-position SIMM connection scheme and requires no additional circuitry.
READ MODE
The DS38464 executes a read cycle whenever WE\ is inactive (high) and CE\ and OE\ are active (low). The unique address specified by the 16 address inputs (A0 - A15) defines which byte of data is to be accessed from the selected SRAMs. Valid data will be available to the data output drivers within tACC (Access Time) after the last address input signal is stable, providing that CE\ and OE\ access times are also satisfied. If OE\ and CE\ access times are not satisfied, then data access must be measured from the later occurring signal (CE\ or OE\) and the limiting parameter is either tCO for CE\ or tOE for OE\ rather than tACC.
WRITE MODE
The DS38464 executes a write cycle whenever both WE\ and CE\ signals are in the active (low) state after address inputs are stable. The later occurring falling edge of CE\ or WE\ will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE\ or WE\. All address inputs must be kept valid throughout the write cycle. WE\ must return to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The OE\ control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output drivers are enabled (CE\ and OE\ active) then WE\ will disable the outputs in tODW from its falling edge.
DATA RETENTION MODE
The DS38464 provides full functional capability for VCC greater than 3.0 volts and write protects by 2.8 volts. Data is maintained in the absence of VCC without any additional support circuitry. The nonvolatile static RAM constantly monitors VCC. Should the supply voltage decay, the NV SRAM automatically write protects itself, all inputs become "don't care," and all outputs become high impedance. As VCC falls below approximately 2.5 volts, power switching circuits connect the lithium energy sources to the RAMs to retain data. During power-up, when VCC rises above approximately 2.5 volts, the power switching circuits connect external VCC to the RAMs and disconnects the lithium energy source. Normal RAM operation can resume after VCC exceeds 3.0 volts.
BATTERY MONITORING
The DS38464 automatically performs periodic battery voltage monitoring on a 24 hour time interval. Such monitoring begins within tREC after VCC rises about VTP and is suspended when power failure occurs. After each 24 hour period has elapsed, the battery is connected to an internal 1MW test resistor for one second. During this one second, if battery voltage falls below the battery voltage trip point (2.6V), the battery warning output BW\ is asserted. Once asserted, BW\ remains active until the SIMM is replaced. The battery is still retested after each VCC power-up, even if BW\ is active. If the battery voltage is found to be higher than 2.6V during such testing, BW\ is de-asserted and regular 24-hour testing resumes. BW\ has an open drain output driver.
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DS38464
PIN ASSIGNMENT
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SIGNAL NAME NC DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 BW\ CEA\ OE\ WE\ DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 VCC A0 VSS PIN 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 SIGNAL NAME A15 A1 A2 A3 A4 A5 A6 A7 DQ16 VCC DQ17 DQ18 VSS DQ19 DQ20 DQ21 DQ22 DQ23 NC A8 A9 VCC VSS A10 PIN 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 SIGNAL NAME A11 VSS NC A12 A13 A14 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 VSS
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DS38464
BLOCK DIAGRAM
VCC A0-18 WE OE A0-A15 VCC WE DQO-DQ7 OE CE 64K X 16 SRAM DQ8-DQ15 VCCO VCCI VBAT BR1632 BW BW
DS1314S-2
CEO CEI
A0-A15 VCC WE OE 64K X 16 SRAM CE DQ16-DQ23 DQ24-DQ31
CEA A0-15 WE DQ32-DQ39 OE 64K X 16 SRAM CE VCC
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DS38464
ABSOLUTE MAXIMUM RATINGS*
Voltage on any pin relative to ground Operating temperature Storage temperature -0.3 to +4.6V 0C to 70C -40C to +85C
*This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER Power Supply Voltage Logic 1 Input Voltage Logic 0 Input Voltage SYMBOL VCC VIH VIL MIN 3.0 2.2 0.0 TYP 3.3 MAX 3.6 VCC +0.4
(TA = 0 to 70C)
UNITS V V V NOTES
DC ELECTRICAL CHARACTERISTICS
PARAMETER Input Leakage Current Output Leakage Current Operating Current Standby Current Output High Current Output Low Current Write Protection voltage SYMBOL IIL ILO ICCO ICCS IOH IOL VTP
TEST CONDITIONS 0V < VIN < VCC 0V < VOUT < VCC, all CE \ = VIH duty=100% all CE\ = VIL, II/O=0, VIN=VIH or VIL all CE\ = VIH VOH = 2.4V VOL = 0.4V
(TA = 0 to 70C; VCC = 3.3V 0.3V)
MIN -4 -1 TYP MAX +4 +1 300 1 -1.0 2.1 2.8
UNITS mA mA mA mA mA mA V
2.9
3.0
CAPACITANCE
PARAMETER Input Capacitance Output Capacitance SYMBOL CIN CI/O MIN TYP MAX 24 10
(TA = 25C)
UNITS pF pF NOTES
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AC ELECTRICAL CHARACTERISTICS (TA = 0 to 70C; VCC = 3.3V 0.3V)
PARAMETER Read cycle time Access time OE to output valid CE to output valid OE or CE to output active Deselection to output high-z Output hold after address change Write cycle time Write pulse width Address setup time Write recovery time WE active to output high-z WE inactive to output active Data setup time Data hold time SYMBOL tRC tACC tOE tCO tCOE tOD tOH tWC tWP tAW tWR1 tWR2 tODW tOEW tDS tDH1 tDH2 MIN 70 TYP MAX 70 35 70 5 25 5 70 55 0 5 20 25 5 30 0 20 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES
5 5
3 11 12 5 5 4 11 12
TIMING DIAGRAM: READ CYCLE
tRC ADDRESS tACC tCO CE tOD OE tCOE DOUT tOE tCOE tOD data valid tOH
SEE NOTE 1
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DS38464
TIMING DIAGRAM: WRITE CYCLE 1 (WE\ Controlled)
tWC
ADDRESS
tWP CE\ tAW tWR1
WE\ DOUT
tOH
tODW tDS
tOEW tDH1
DIN
data valid
SEE NOTES 2, 3, 4, 6, 7, 8 AND 11
TIMING DIAGRAM: WRITE CYCLE 2 (CE\ Controlled)
tWC ADDRESS tAw tWP CE\ tWR2
WE\
tODW tCOE DOUT tDS DIN tDH2
data valid
SEE NOTES 2, 3, 4, 6, 7 8 AND 12
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DS38464
TIMING DIAGRAM: POWER-DOWN AND POWER-UP
VCC VTP ~2.7V tF tPD CE\, WE\ tPU tR tREC
BACKUP CURRENT SUPPLIED FROM LITHIUM BATTERY
tDR
SEE NOTE 10
POWER-DOWN/POWER-UP TIMING
PARAMETER VCC Fail Detect to CE\ and WE\ Inactive VCC Slew from VTP to 0V VCC Slew from 0V to VTP VCC Valid to CE\ and WE\ Inactive VCC Valid to End of Write Protection SYMBOL tPD tF tR tPU tREC MIN 150 150 2 125 TYP MAX 1.5
(TA = 0 to 70C)
UNITS ms ms ms ms ms NOTES 10
(TA = 25C)
PARAMETER Expected Data Retention Time SYMBOL tDR MIN 6 TYP MAX UNITS years NOTES 9
WARNING
Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery backup mode.
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DS38464
NOTES
1. WE\ is high throughout read cycle. 2. OE\ = VIH or VIL. If OE\ = VIH during write cycle, the output buffers remain in a high impedance state. 3. tWP is specified as the logical AND of CE\ and WE\. tWP is measured from the latter of CE\ or WE\ going low to the earlier of CE\ or WE\ going high. 4. tDS is measured from the earlier of CE\ or WE\ going high. 5. These parameters are sampled with a 5 pF load and are not 100% tested. 6. If the CE\ low transition occurs simultaneously with or later than the WE\ low transition, the output buffers remain in a high impedance state during this period. 7. If the CE\ high transition occurs prior to or simultaneously with the WE\ high transition, the output buffers remain in a high impedance state during this period. 8. If WE\ is low or the WE\ low transition occurs prior to or simultaneously with the CE\ low transition, the output buffers remain in a high impedance state during this period. 9. Each DS38464 has a built-in switch that disconnects the lithium source until VCC is first applied by the user. The expected tDR is defined as accumulative time in the absence of VCC starting from the time power is first applied by the user. 10. In a power down condition the voltage on any pin may not exceed the voltage on VCC. 11. tWR1, tDH1 are measured from WE\ going high. 12. tWR2, tDH2 are measured from CE\ going high. 13. BW\ is an open-drain output and cannot source current.
DC TEST CONDITIONS
Outputs Open Cycle = 200 ns All voltages are referenced to ground
AC TEST CONDITIONS
Output load: 50 pF + 1 TTL gate Input pulse levels: 0 V to 2.7 V Timing measurement reference levels input: 1.5 V output: 1.5 V Input pulse rise and fall times: 5 ns
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DS38464
DS38464 72-PIN SIMM MODULE
A J B N
C D E H G
1
72
Battery + NV controller side + SRAMs
M I K L I
F
O
PKG DIM A B C D E F G H I J K L M N O
INCHES MIN MAX 4.245 4.255 3.979 3.989 0.845 0.855 0.395 0.405 0.245 0.255 0.050 BSC 0.075 0.085 0.245 0.255 1.750 BSC 0.120 0.130 2.120 2.130 2.245 2.255 0.057 0.067 0.130 0.047 0.054
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